Links on this page will take you to articles posted on the web on topics that are relevant to SerDes system design.<\/p>\n
Let us know if there are other links you would like to add to this list.<\/p>\n
IBIS Version 7.0<\/a> was ratified by the IBIS Open Forum on March 15, 2019, with inclusion of Rx to Tx back channel support.<\/p>\n IBIS Version 6.1<\/a> was ratified by the IBIS Open Forum on September 11, 2015, with more clarifications and extensions to the AMI format, including support for PAM4 SerDes systems.<\/p>\n IBIS Version 6.0<\/a> was ratified by the IBIS Open Forum on September 20, 2013, with more clarifications and extensions to the AMI format, including support for SerDes system redrivers and retimers.<\/p>\n Touchstone 2.0<\/a> file format specification for representing the frequency domain characteristics for N-port high frequency structures. Only the 1.0 file format described in the file is supported in the serdesdesign.com tools.<\/p>\n 1. Topics on High Speed Links – Introduction<\/a> Links on this page will take you to articles posted on the web on topics that are relevant to SerDes system design. Let us know if there are other links you would like to add to this list. IBIS Version 7.0 was ratified by the IBIS Open Forum on March 15, 2019, with inclusion of […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"nf_dc_page":"","footnotes":""},"class_list":["post-87","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/pages\/87","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/comments?post=87"}],"version-history":[{"count":5,"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/pages\/87\/revisions"}],"predecessor-version":[{"id":1178,"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/pages\/87\/revisions\/1178"}],"wp:attachment":[{"href":"https:\/\/www.serdesdesign.com\/home\/wp-json\/wp\/v2\/media?parent=87"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\n2. Channel Components, Wires, & Transmission Lines<\/a>
\n3. Transmission Lines<\/a>
\n4. Transmission Line Examples<\/a>
\n5. Interconnect Measurement Techniques<\/a>
\n6. S-Parameter Channel Examples<\/a>
\n7. Channel Time-Domain Response<\/a>
\n8. Channel Pulse Model<\/a>
\n9. Modulation Schemes<\/a>
\n10. Termination & Transmitter Circuits<\/a>
\n11. Transmitter Circuits<\/a>
\n12. TX Multiplexer Circuits<\/a>
\n13. RX Circuits<\/a>
\n14. RX Comparator Circuits<\/a>
\n15. RX Circuits<\/a>
\n16. Equalization Introduction<\/a>
\n17. TX FIR Equalization<\/a>
\n18. RX FIR & CTLE Equalization<\/a>
\n19. RX DFE Equalization<\/a>
\n20. Noise Sources<\/a>
\n21. Crosstalk<\/a>
\n22. ISI and Random Noise<\/a>
\n23. Jitter<\/a>
\n24. Jitter Budget & Stateye<\/a>
\n25. Clocking Architectures<\/a>
\n26. Phase-Locked Loops<\/a>
\n27. PLL Circuits<\/a>
\n28. VCOs<\/a>
\n29. PLL Wrap-Up<\/a>
\n30. CDRs<\/a>
\n31. CDR Architectures<\/a>
\n32. CDR Wrap-Up<\/a>
\n33. Optical I\/O<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"