High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems. In such systems, a Channel Simulator is used to simulate SerDes systems based on the IBIS-AMI standard.
This paper discusses the use of multi-core CPUs to significantly reduce PAM4 system simulation time required for a Channel Simulation to achieve accurate BER results at low levels.
See the full article: Channel_Simulation_PAM4_System_MultiCore_Tests.pdf
About John Baprawski
Hi. I am John Baprawski. I have been a successful electronic system design engineer in the communications and radar product development industries for over 30 years and I can help you meet your product design objectives.
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